Upcoming Implementation Of ProgPow For Ethereum Algorithm Gains Support From Majority Of Voters

The current roadmap for Ethereum shows that there are certain upgrades and milestones that the platform aims to reach over a 4-stage plan. The most recent stage is set to include a newly integrated type of PoW (proof of work) algorithm called ProgPoW. The algorithm is resistant to ASIC use and it will be used in place of the current algorithm, ETHhash. A new online vote through Ethereum shows that the majority of their voters are in favor of this change.

Since the algorithm will be ASIC resistant, developers will see a decrease in the efficiency of using ASICs over the generic hardware that could be used to mine, which essentially means that graphics processing units will be used. However, this update does not completely eliminate the use of ASICs.

The numbers on the Ethereum platform indicate that there’s over 76% of votes (628,000 ETH, which is about $76 million). There are 23% of voters, which accounts for 191,000 ETH ($23 million) that were against it.

According to the voting portal, the token holders are the ones that will take on the most impact from the changes made with the algorithm. By allowing ETH holders to vote, the developers can get a clearer idea of what the community wants than taking into account the comments that are anonymously posted in online forums. At this point, there is no timeframe for the end of the voting process, and the election results do not place any requirements on the voters.

A consensus in the implementation of the algorithm was reached earlier last month, determining that the developers would delay the implementation. This delay gave them time to let the algorithm be audited by a third party at the beginning of this month.

Unfortunately, ProgPoW has faced a lot of controversies since it was announced, due to a post from a code contributor at Ethereum that said developers should embrace the use of ASICs. However, other members of Ethereum believe that the algorithm will not give the ASIC resistance that they expect.

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